The present invention relates to layout of conductive features in microelectronic components. Some embodiments provide capacitors and electromagnetic shields for microelectronic components.
Capacitors are widely used in electronic circuitry for charge storage (e.g. in memories and power supplies), band-pass filtering (in radio receivers) and for other purposes. A capacitor includes two conductive capacitor electrodes (also called capacitor plates even though they may or may not be flat) separated by dielectric. A simple way to increase the capacitance is to increase the plates' area, but this may undesirably increase the lateral area of the microelectronic component.
One way to increase the capacitor area without increasing the lateral area of an integrated circuit (IC) is to form upward protrusions (fins) of semiconductor material over the IC's substrate, and cause capacitor plates to curve over the fins. FIG. 1 shows such structure as described in U.S. pre-grant patent publication no. 2011/0291166 (Dec. 1, 2011; inventors Booth, Jr. et al.). Fin 50 is formed of a semiconductor layer on dielectric 54 on substrate 58. Dielectric 60, conductor 64, dielectric 68, and conductor 72 are formed over the fin. Conductors 64 and 72 serve as capacitor plates, and dielectric 68 is a capacitor dielectric. Additional fins (not shown) are formed of the same layer as fin 50 to provide transistor regions for fin FETs (filed effect transistors).
The capacitor and the transistors are covered by dielectric 74. Contacts 76 provide access to the capacitor plates.
In a variation, a fin can serve as one of the capacitor electrodes. See also U.S. Pat. No. 8,841,185 (Sep. 23, 2014, Khakifirooz et al.).
Another way to increase the capacitor area is to use opposite sides of the substrate. FIG. 2A illustrates such a scheme described in U.S. Pat. No. 8,373,252 issued Feb. 12, 2013 to DeBaets. Integrated circuit 102 has a semiconductor substrate 104 with transistors (not shown) at the top. Metal lines 110G and 110P are formed at the top to carry respectively a ground voltage and a power supply voltage to the transistors. These lines are connected to respective conductive through-vias 114G, 114P arranged in respective through-holes 118 passing through the substrate 104. Vias 114G, 114P are connected to respective capacitor electrodes 120E.G, 120E.P of a decoupling capacitor 120 formed at the bottom of substrate 104. The capacitor electrodes are flat plates separated by capacitor dielectric 120D. Plate 120E.G surrounds the protrusion of via 114P. Capacitor 120 provides a low-impedance path for high-frequency components of certain signals in the integrated circuit. IC 102 has multiple capacitors 120 (only one of which is shown) at the bottom, and the capacitor area is limited by the lateral area of the IC. See also U.S. Pat. No. 7,851,321 (Clevenger et al., Dec. 14, 2010).
Integration of capacitors with circuits at opposite sides of a substrate is highly desirable for interposers; an interposer provides interconnection between circuits above and below the interposer. FIG. 2B shows a decoupling capacitor scheme for an interposer as described in U.S. Pat. No. 7,510,928 (Savastiouk et al., Mar. 31, 2009). The capacitor 120 is manufactured in interposer 210 provided between integrated circuits 102 and a printed circuit board (PCB) 220. The capacitor's electrodes 120E (shown as 120E.A, 120E.B) are planar electrodes formed over the interposer's substrate 104. Electrodes 120E are separated from each other by dielectric (not shown). Conductive vias 114A, 114B pass through the substrate 104 by way of respective through-holes 118. The vias 114A, 114B carry power and ground voltages from the PCB to the ICs. Via 114A is connected to capacitor plate 120E.A, but passes through a hole in plate 120E.B without contacting the plate. Similarly, via 114B is connected to plate 120E.B, but passes through a hole in plate 120E.A without contacting the plate.
Via 114C carries electrical signals between PCB 220 and ICs 102. Via 114C passes through hole 118 in substrate 104, and passes through capacitor plates 120E.A and 120E.B without contacting the two plates.
Vias 114A, 114B, 114C are connected to conductive lines 230 above the capacitor. Conductive lines 230 are attached to ICs 102.
In this scheme, the capacitor area is limited by the lateral size of substrate 104 and by the room taken by the holes made in the capacitor plates for vias 114.
Another possibility is a vertical capacitor (FIG. 3) in a through-hole 118 in an interposer's substrate 104. See U.S. Pat. No. 6,498,381 (Dec. 24, 2002, Halahan et al.). Electrodes 120E are formed as separate frustoconical layers in hole 118; electrode 120E.A is the inner cone, and electrode 120E.B is the outer cone. The electrodes are separated by dielectric 120D. Another frustoconical conductive layer, schematically shown by straight line 114, can provide a conductive path between the top and bottom of the interposer in the same hole 118. Additional frustoconical conductive layers (not shown) in the hole can provide electromagnetic shielding for the conductive path. Such layers are accommodated by making the hole 118 sufficiently wide, but this may undesirably increase the interposer size. The capacitor size can be increased in the vertical dimension but this requires a deeper hole 118 and complicates manufacturing because it is harder to form capacitor layers in deeper holes.
Other schemes are therefore desired for capacitors, EM shielding structures, and other circuitry.